Electron-beam processed films for microelectronics structures

ABSTRACT

An improved method for producing substrates coated with dielectric films for use in microelectronic applications wherein the films are processed by exposing the coated substrate surfaces to a flux of electron beam. Substrates cured via electron beam exposure possess superior dielectric properties, density, uniformity, thermal stability, and oxygen stability.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. provisionalapplication serial No. 60/000,239 filed on Jun. 15, 1995, which isincorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to electron-beam processed filmsfor microelectronics structures, such as integrated circuits (“IC”).More particularly, this invention relates to an improvement in themethod of processing such films which results in uniform, dense films,some of which also possess a low dielectric constant and a low wet etchrate.

[0004] 2. Background of the Invention

[0005] Various devices, such as multichip modules, printed circuitboards, high-speed logic devices, flat panel displays, integratedcircuits and other microelectronics devices, require deposited orspun-on dielectric films.

[0006] One commonly used technique to produce such a desirable film ontoa substrate involves thermal anneal or thermal cure at a temperaturerange between 350° C. and 900° C. for about 1 hour. See “Spin/Bake/CureProcedure for Spin-On-Glass Materials for Interlevel and IntermetalDielectric Planarization” brochure by AlliedSignal Inc. (1994)(thermallycured spun-on films) and Kern, W., “Deposited Dielectrics for VLSI,”8(7) Semiconductor International 122 (July 1985)[“Kern”]; Gorczyca, T.B., et al., “PECVD of Dielectrics,” 8(4) VLSI Electronics MicrostructureScience (New York 1984)[“Gorczyca”]; and Mattson, B., “CVD Films forInterlayer Dielectrics,” Solid State Technology 60 (January1980)[“Mattison”](thermally annealed chemical vapor deposited (“CVD”)films). However, several disadvantages are associated with thermalprocessing.

[0007] In applications wherein a spin-on glass film (“SOG”) is spun ontoa substrate, siloxane-type SOGs are susceptible to damage by oxygenplasmas. During subsequent IC processing, SOGs which have been damagedby oxygen plasma are prone to outgassing of moisture, which often leadsto electrical and mechanical reliability failures. In addition, thethermally cured SOGs' instability to oxygen plasma also contributes notonly to manufacturing difficulties such as delamination, but also tophysical, mechanical and cosmetic deficiencies in the final product suchas increased porosity, increased shrinkage, and poor planarization.

[0008] Second, the use of such high temperatures for curing silicateSOGs also causes the oxidation and degradation of silicides. This oftenleads to device failures caused by silicide degradation or degradationof the shallow dopant profiles in advanced ICs. Further, the presence ofthis oxidized surface layer disadvantageously affects the overallelectrical performances of the IC by increasing the resistance orremoving the electrical contact to suicides as well as by contributingto degradation of interconnections between transistors.

[0009] In applications wherein the substrate is coated with a CVD film,an additional annealing step at high temperatures up to about 1000° C.is also required in order to improve the quality of the CVD film.However, this leads to complications and device failure problems such assilicide degradation, hot carrier degradation, device instabilities, andthe like. Though these difficulties are similar to those observed withthermal processing, the magnitude of the effects is greater because thetemperatures involved are significantly higher.

[0010] In growing ultra-thin gate oxides and nitrides on substrates, oneknown problem is the inability to control the uniformity of theirgrowth. Prior art methods for growing such oxides employ single waferRapid Thermal Processing systems (“RTP”) or furnaces as described in,for example, Sheets, R., “Rapid Thermal Processing Systems,”Microelectronic Mfg. and Microelectronic Mfg. and Test, 16 (July 1985).However, growth failure will occur in these methods if contaminants arepresent at amounts as low as parts per billion. This inability toproduce such uniform oxides and nitrides often leads to subsequentburning of the oxide or nitride during operation of the IC and thusaffects its overall reliability.

[0011] It is desirable for all advanced ICs to possess a dielectricmaterial having a low dielectric constant. Generally, CVD films do notpossess low dielectric constants unless they are doped with high levelsof fluorine. See Takeshi, S., et al., “Stabilizing Dielectric Constantsof Fluodne-Doped-Silicon Dioxide Films by N ₂ O-Plasma Annealing,”Dielectrics for VLSI/ULSI multilevel Interconnection Conference (DUMIC)(February 1995). However, such fluorine-doped oxides are usuallyunstable and susceptible to degradation in moist and oxygen plasmaenvironments.

[0012] Although a lower dielectric constant may be obtained by usingspin-on polymer-containing films (“SOPs”), such films pose greatchallenges for process integration due to their poor thermal stability,their tendency to degrade when exposed to oxygen plasmas, and theirtendency to decompose at temperatures typically used for metal layerdeposition in ICs. Furthermore, the lowest dielectric constant that canbe achieved for SOGs which have been thermally cured is typically onlyabout 3.8-4.1. Such dielectric values may not be suitable for the enduses of the next generation microelectronic applications due to morestringent controls on mechanical and electrical effects such ascapacitance that are becoming more critical as device dimensions arereduced.

[0013] It would be desirable to provide an improved process for rapidlyprocessing dielectric film coatings on substrates at low temperatureswhich would result in a product that was thermally stable andinsensitive to oxygen plasma. It would also be desirable to provide auniformly dense SOG or CVD material possessing a low dielectricconstant. Moreover, it would be desirable to uniformly grow ultra-thingate oxides on substrates.

SUMMARY OF THE INVENTION

[0014] In accordance with this invention, there is provided animprovement in the curing of a dielectric material on a substratecomprising:

[0015] (a) applying to a surface of the substrate a dielectric material;and

[0016] (b) exposing said dielectric material to electron beam radiationunder conditions sufficient to cure the dielectric material.

[0017] In accordance with another aspect of this invention, there isprovided an improvement in the annealing of a substrate coated with achemical vapor deposited material comprising:

[0018] a) applying to the surface of the substrate the chemical vapordeposited material; and

[0019] b) exposing the chemical vapor deposited material to electronbeam radiation under conditions sufficient to anneal the chemical vapordeposited material.

[0020] In accordance with another aspect of this invention, there isprovided an improvement in the growth of ultra-thin film oxides ornitrides on a substrate comprising:

[0021] a) exposing a surface of the substrate to electron beam radiationin the presence of a material in a gaseous state and under conditionssufficient to ionize the material and promote an oxidization ornitridation reaction on the surface of the substrate.

[0022] In accordance with yet another aspect of this invention, there isprovided a substrate coated with an electron beam processed filmproduced according to the above processes.

[0023] In accordance with another aspect of this invention, there isprovided a process for reducing the dielectric constant in dielectricfilm and chemical vapor deposit film coated substrates comprised ofexposing said film to electron beam radiation under conditionssufficient to process said film.

[0024] In accordance with another aspect of this invention, there isprovided a process for producing silicon rich films from chemical vapordeposit coatings comprised of exposing said coatings to electron beamradiation under conditions sufficient to process said film.

[0025] In yet another embodiment of this invention, there is provided amicroelectronic device containing a substrate coated with anelectron-beam processed film, wherein the dielectric constant of saidelectron-beam processed film is less than about 3.

[0026] The electron-beam processed films of this invention not onlyadvantageously form a dense, uniform coating on substrates, but alsoelectron beam cured SOG films possess a dielectric constant which issignificantly lower than that reported for similar compositions whichwere thermally treated at high temperatures. Moreover, the time andtemperature for processing such films is significantly reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The invention will be more fully understood and furtheradvantages will become apparent when reference is made to the followingdetailed description of the invention and the accompanying drawings inwhich:

[0028]FIG. 1 is a graph of absorbance versus wave number (cm⁻¹) for theFourier Transform Infrared Spectra (“FTIR”) of siloxane SOG coatedwafers which were either hot plate baked, thermally cured orelectron-beam cured.

[0029]FIG. 2(a) and (b) are graphs of absorbance versus wave number(cm⁻¹) for the FTIR spectra of siloxane SOG coated wafers cured withelectron beams at various beam doses and cure temperatures.

[0030]FIG. 3 is a graph of percent film shrinkage versus electron beamdose (PC/cm²) for siloxane SOG coated wafers cured via thermally and byelectron beam radiation.

[0031]FIG. 4 is a graph of percent film shrinkage versus electron beamenergy (KeV) for electron-beam cured siloxane SOG coated wafers.

[0032]FIG. 5 is a graph of wet etch rate (Å/sec) in buffered oxide etch(“B.O.E.”) 50:1 for thermally cured SOG coated wafers, for thermal oxidewafers and for electron beam cured SOG coated wafers as a function ofelectron beam dose (μC/cm²).

[0033] FIGS. 6(a)-(d) are graphs of wet etch rate (Å/sec) in B.O.E. 50:1as a function of the depth of film thickness (Å) for electron-beam curedSOG coated wafers.

[0034]FIG. 7 is a graph of the wet etch rate (Å/sec) in B.O.E. 50:1 as afunction of the depth of film thickness (Å) for electron-beam cured SOGcoated wafers at various degrees of electron beam energy (KeV).

[0035]FIG. 8 is a graph of absorbance versus wavenumber (cm⁻¹) for theFTIR spectra of electron-beam cured SOG coated wafers after completionof various stages of processing.

[0036]FIG. 9 is a graph of absorbance versus wavenumber (cm⁻¹) for theFTIR spectra of a thermally cured SOG film and for an electron beamcured SOG film which were both exposed to post cure ambient conditions.

[0037] FIGS. 10(a) and (b) are graphs of absorbance versus wavenumber(cm⁻¹) for the FTIR spectra of electron beam cured SOG coated wafersafter electron-beam cure, as well as after electron beam cure followedby immersion in water, respectively.

[0038]FIG. 11 is a graph of absorbance versus wavenumber (cm⁻¹) for theFTIR spectra for aged films cured with electron beams in the presence ofvarious gases.

[0039]FIG. 12 is a graph of cumulative probability of time to breakdown(“QBD”) versus time to breakdown (seconds) of a gate oxide with atetra-ethyl orthosilicate (“TEOS”)-capped electron-beam cured SOG.

[0040]FIG. 13 is a graph of depth (microns) versus concentration(atoms/cc) for secondary ion mass spectroscopy (“SIMS”) depth profileanalysis for Na, K, H, C, and O impurities though the said oxidethickness.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] Unless indicated otherwise, all references herein are specifiedin weight. “Dose” as used herein shall refer to doses of electron beamradiation.

[0042] Various materials may be applied onto the substrates of thepresent invention via “spinning-on”, CVD, or growing techniques.

[0043] Suitable dielectric materials or SOG which may b spun-on tosubstrates include silicates, phosphosilicates, siloxanes,phosphosiloxanes, and mixtures thereof. Siloxanes are preferred, Morepreferable siloxanes are amorphous, crosslinked glass-type materialshaving the formula SiO_(x) wherein x is greater than or equal to one andless than or equal to two, and possess a “pre-exposure” content, basedupon the total weight of the siloxane materials, of from about 2% toabout 90%, and preferably from about 10% to about 25% of organic groupssuch as alkyl groups having from about 1 to about 10 carbons, aromaticgroups having from about 4 to about 10 carbons, aliphatic groups havingfrom about 4 to about 10 carbons, and mixtures thereof. Optionally, thesiloxane and silicate materials may also contain, based upon the totalmole percent of the dielectric materials, from about 0% to about 10%,and preferably from about 2% to about 4% phosphorus.

[0044] Preferred siloxane materials suitable for use in this inventionare commercially available from AlliedSignal Inc. under the tradename“Accuglass”®.

[0045] Suitable siloxane materials contain about 100 parts per billionor less, preferably 50 parts per billion or less, and more preferably 10parts per billion or less of trace element impurities such as sodium,potassium, chlorine, nickel, magnesium, chromium, copper, manganese,iron, calcium, and the like, and preferably have a molecular weightbetween from about 300 to about 50,000, and more preferably from about500 to about 10000 molecular weight units.

[0046] The dielectric material may be applied to substrates viaconventional spin-coating, dip coating, spraying, or meniscus coatingmethods well-known in the art. Details of such methods are described in,for example, “Processing Equipment and Automated Systems”, brochure byIntegrated Technologies.

[0047] The thickness of the dielectric film on the substrate may varydepending upon the amount of SOG liquid that is applied to thesubstrate, but typically the thickness may range from about 500 Å toabout 20000 Å, and preferably from about 3000 Å to about 9000 Å. Theamount of SOG liquid applied to the substrate may vary between fromabout 1 ml to about 10 ml, and preferably from about 2 ml to about 8 ml.

[0048] In a preferred embodiment, the siloxane material is centrallyapplied to a substrate, which is then spun at speeds ranging betweenabout 500 and about 6000 rpm, preferably between about 1500 and about4000 rpm, for about 5 to about 60 seconds, preferably about 10 to about30 seconds, in order to spread the solution evenly across the substratesurface.

[0049] Suitable materials which may be deposited onto substrates via CVDinclude plasma-enhanced tetra-ethyl ortho silicate (“PETEOS”), silanebased oxides such as silane and di-silane, boron-phosphosilicate glass(“BPSG”), phosphosilicate glass (“PSG”), nitrides such as siliconnitride (SiN) and non-stoichiometric mixtures therewith, anhydridefilms, oxynitrides such as those deposited with silane (SiH₄), ammonia(NH₃), nitrogen, and nitrous oxide (N₂O) and mixtures thereof, andborophospho glass from tetraethyl orthosilane (“BPTEOS”), and mixturesthereof. Silane-based oxide films are preferred.

[0050] The CVD film may be applied to the substrate in the presence of agas via conventional CVD methods well-known in the art. Details of suchmethods are well known in the art and are described in, for example,Gorczyca; Kern, and Mattison, which are incorporated herein byreference. The gas selected for CVD applications depends upon the typeof film desired, but typically such gases include a mixture of TEOS andoxygen, or a mixture of oxygen, silane and optionally diborane (“B₂H₆”), phosphine (“PH 3”), and nitrous oxide (“N 20”), and preferablyTEOS.

[0051] The amount of CVD coating deposited onto the surface of thesubstrate is proportional to the film thickness desired and may rangefrom about 1000 Å to about 30000 Å, and preferably from about 3000 Å toabout 8000 Å. The amount of CVD applied to the substrate may varyaccording to the film thickness desired. Gas flows required to obtainthese thicknesses are described in Kern; Gorczyca; and Mattison.

[0052] Typically, the SOG or CVD films are applied onto, and theultra-thin oxide or nitride films are grown on a wafer or other planarsubstrate, such as silicon wafers which have a circuit pattern on theirsurface, to be processed into ICs or other microelectronic devices.Typically, the diameters of the substrates range from about 2 inches toabout 12 inches, although the present invention would still be effectivefor larger substrates.

[0053] Optionally, the pre-cured SOG-coated substrate may be heated at atemperature of about 50° C. to about 250° C. for about 1 to about 3minutes. In a preferred embodiment, the pre-cured SOG is first heated atabout 50° C. for about 30 seconds to one minute, then heated at about150° C. for about 30 seconds to one minute, and heated a third time atabout 250° C. for about 30 seconds to one minute. The pre-cured liquidSOG material partially crosslinks and solidifies as a result of suchheating.

[0054] The SOG coated substrate is cured by exposing the surface of thesubstrate to a flux of electrons while in the presence of a gas selectedfrom the group consisting of oxygen, argon, nitrogen, helium andmixtures thereof, and preferably oxygen, argon, nitrogen, and mixturesthereof. Nitrogen gas is more preferred.

[0055] The temperature at which the electron beam exposure is conductedwill depend on the desired characteristics of the resulting film and thelength of desired processing time. One of ordinary skill in the art canreadily optimize the conditions of exposure to get the claimed resultsbut the temperature will generally be in the range of about 25° C. toabout 400° C. The pressure during electron beam curing will rangebetween from about 10 mtorr to about 200 mtorr, and preferably fromabout 10 mtorr to about 40 mtorr.

[0056] The period of electron beam exposure will be dependent upon thecurrent density and the beam dosage to be applied to the substrate. Oneof ordinary skill in the art can readily optimize the conditions ofexposure to get the claimed results, but generally the exposure willrange from about 2 to about 45 minutes, and preferably from about 5 toabout 25 minutes with application of an electron beam dose of about 1000to about 50,000, preferably from about 2500 to about 10,000 μC/cm². Theaccelerating voltage of the electron beam may vary from about 1 to about25 KeV. The amount of dose and the accelerated voltage selected will bedependent upon the characteristic and thickness of the films to beprocessed.

[0057] The coated SOG substrate may be exposed to electron beams in anychamber having a means for providing electron beam radiation tosubstrates placed therein. Typically, the chamber is also equipped witha means for emitting electrons into a gaseous atmosphere comprisingoxygen, argon, nitrogen, helium and mixtures thereof, and preferablyoxygen, argon, and nitrogen, simultaneously with electron beam exposure.

[0058] In a preferred embodiment, the coated SOG substrate is placedinto a chamber which is commercially available from Electron Vision, SanDiego, Calif., under the tradename “ElectronCure”™, the principles ofoperation and performance characteristics of which are described in U.S.Pat. No. 5,001,178, which is incorporated herein by reference. Thischamber beneficially provides a “wide, large beam” of electrons whichmay affect an area of from about 4 to about 144 square inches.

[0059] Similarly, CVD coated films are annealed via the same process andunder the same conditions as described for curing SOG coated substrates.

[0060] For applications in which ultra-thin gate oxides or nitrides aregrown on substrates, the type of film which is grown depends upon thecomposition of the substrate and the substance grown in the gaseousstate selected. Any compositions such as gallium arsenide (GaAs) orcompositions containing silicon such as crystalline silicon,polysilicon, amorphous silicon, or epitaxial silicon, and preferablysilicon dioxide (SiO₂) are suitable substrate materials. The growth ofthe oxides or nitrides occurs in the presence of oxygen, ammonia,nitrogen, nitrous oxide, and reaction products and mixtures thereof inthe form of a gas, a sublimed solid or a vaporized liquid. Oxygen gas ispreferred.

[0061] According to the present invention, the oxide or nitride ultrathin film layer is grown on the substrate surface simultaneously withthe period in which it is exposed to electron beams in the presence of agas. The period of electron beam exposure occurs for a time sufficientto allow the gas to both ionize and react with the compounds present onthe surface of the substrate. The thickness of the grown films may rangefrom about 10 Å to about 1000 Å, and preferably from about 50 Å to about80 Å. Otherwise, the process and conditions for growing such oxide ornitride ultra thin film layers are similar to those described for curingSOG coated substrates. As a result, both the uniformity of thecomposition and thickness of the ultra-thin oxide or nitride films grownon the substrate is improved.

[0062] As a result of exposing a coated substrate to electron beamradiation according to the present invention, the films produced thereonare unexpectedly modified into a new, unique chemical form. For example,“FTIR” analysis reports that there are no longer CH groups attached tothe backbone of SOG starting compounds after they are cured withelectron beams. However, Secondary Ion Mass Spectroscopy (“SIMS”)analysis demonstrates that the carbon remains in the film. In comparisonto thermally-cured coatings which possess oxidized carbon in the top0.05 to 0.3 microns of the cured coatings or films, the carbon in thecured siloxane SOG and carbon-containing SOP coatings of the presentinvention is homogeneously distributed throughout the film.

[0063] The substrates coated with a film processed according to thepresent invention may be used for any dielectric and planarizationapplication in microelectronics fabrication. One noteworthycharacteristic of the SOG coatings processed according to the presentinvention is that they exhibit excellent dielectric properties withouthaving to add additional polymers thereto. Dielectric properties of theSOG or SOP coatings cured according to the present invention rangedbetween about 2.5 to about 3.3, and preferably between about 2.9 toabout 3.0.

[0064] Another noteworthy characteristic of the films processedaccording to the present invention is that their density increasessignificantly as a result of the step of electron beam processing. Inaddition, the processed film coatings not only have a wet etch rate inBuffered Oxide Etch “BOE” 50:1 which is comparable to that recorded forthermal oxides, but there films also are resistant to oxygen plasmas,are able to be chemically and mechanically polished with gooduniformities, and are able to withstand the temperature budgetassociated with typical W plug processing. More specifically, thesiloxane coatings cured according to the present invention andsubsequently exposed to nitrogen at 425° C. for one hour shrunk only 4%,and no additional shrinkage occurred when the films were exposed for upto 1 hour at 700° C.

[0065] For deposited oxides, the invention provides a means for creatingdensified films without employing high temperature anneals. Morespecifically, index of refraction analysis reveals that the result ofannealing CVD films comprised of PETEOS according to the process of thepresent invention is a “silicon-rich” film which is unobtainable throughother known means in the art such as modification of the gas ratiosduring film deposition or thermal annealing. This is especiallybeneficial because such “silicon-rich” films are known to prevent fieldinversion and hot electron degradation effects.

[0066] Moreover, not only are the temperatures at which the processingof the present invention occurs significantly below those employed inprior art thermal curing or annealing processes, but the time for curingor annealing such films is also significantly reduced.

[0067] The use of this invention also results in an improved ultra-thinfilm oxide or nitride coating for substrates whereby the growth of suchoxides or nitrides may be controlled.

[0068] The present invention may be incorporated into several knownprocesses such as: 1) disposable post processing; 2)conventionally-etched contact processing; and 3) inter-metal dielectricprocessing.

[0069] The following non-limiting examples illustrate the effect ofexposing coated substrates to electron beam radiation in order to createa film having improved characteristics thereon.

[0070] The films produced in the following examples were analyzedaccording to the following test methods:

[0071] 1) Film Thickness: Using a calibrated Nanospec® AFT model 010-180computerized Film Thickness Measurement System available fromNanometrics, Co., wavelengths from about 480 nm to 790 nm were scannedthrough the wafer and converted to Angstroms (Å) via its internalcomputer. Measurements were acquired for five different locations on thewafer, then these five values were averaged.

[0072] 2) Percent Film Shrinkage: This value is obtained from a ratio ofthickness measurements obtained according to the procedure described inFilm Thickness and recorded after various processing steps.

[0073] 3) Wet Etch Rate Determination: Details for conducting this testare set forth in “Relative Etch Rate Determination”, a report byAlliedSignal Inc., Advanced Microelectronic Materials Division (November30, 1994).

[0074] 4) Dielectric Constant: The dielectric constant of SOG films isdetermined by the standard capacitance-voltage (“CV”) curve technique,using metal-oxide semiconductor (“MOS”) capacitor structures as would beused for any other dielectric thin films. The dielectric constant iscalculated from the C(max)/C(oxide) derived from the CV curve, thicknessof the film being measured, and the capacitor plate (Al dot) area.

[0075] A Hewlitt Packard Model 4061A semiconductor measurement systemconsisting primarily of a sensitive multifrequency (10 Khz-10 Mhz)Induction Capacitance and Resistance (“LCR”) meter, current and voltagesources, ramp generator, and picoammeter was used to measure the CVcurve of dielectric films. The measurement, calculation, and plottingfunctions are carried out by a dedicated Hewlitt Packard microcomputerthrough an IEEE-488 standard interface bus. Substrates are probed on amanual probe station placed inside a metal dark-box. Further details ofthis procedure are set forth in “SOG Dielectric Constant Theory”, reportby AlliedSignal Inc., Advanced Microelectronic Materials Division (Jan.3, 1995).

[0076] 5) Index of Refraction: This value is determined using acalibrated AutoEL II® Revision 307 ellipsometer available from RudolphResearch. Calibration and measurement procedures are described in“AutoEL II Revision 307 Ellipsometer Calibration and Maintenance”,report by AlliedSignal, Inc., Advanced Microelectronic MaterialsDivision (Jun. 5, 1995).

[0077] 6) Fourier Transform Infrared Spectrum Analysis: Fouriertransform infrared spectrum analysis reveals vibrations of atoms inmolecules. Certain groups of atoms have characteristic vibrationfrequencies which persist in different compounds. Details such as thefrequency position of infrared bands characteristic of someorganosilicon groups, are described in, for example, Launer, “InfraredAnalysis of Organosilicon Compounds: Spectra-structure Correlations”,(Burnt Hills, N.Y., 1990).

[0078] 7) Contact Resistance: Contact Resistance procedure is describedin Loh, W. M., et al., “Modeling and Measurement of Contact Resistances”IEEE Transactions Electron Devices 512 (March 1987).

[0079] 8) Device and Field Threshold Voltages and Transistor Voltages(Vts): These voltage measurements and techniques for obtaining suchmeasurements similar to those employed in the Examples are described inAndoh, T., et al., “Design Methodology for Low Voltage MOSFETS” Int'l.Electron Device Meeting (December 1994).

[0080] 9) Time to Breakdown (“QBD”): This procedure is described inGrove, Physics & Technology of Semiconductor Devices, Section 10.5 (NewYork 1967); Chen, K. L., et al., Tech. Digest IEDM 484 (1986),; andRountree, R. N., Tech. Digest IEDM 580 (1988).

[0081] 10) Via resistance: Via resistance was measured using techniquesdescribed in “Pre-sputter Degassing Treatment in Via Contact for ViaReliability Enhancement in Spin-On Glass Plananization Process” forVLSI/ULSI Multilevel Interconnection Conference (February 1995).

[0082] 11). Resistance and Silicide Resistance: Silicide resistance wasmeasured using techniques described in Shimizu, S., et al., “0.15 μmCMOS Process for High Performance and High Reliability,” InternationalElectron Device Meeting (December 1994).

[0083] 12) Secondary Ion Mass Spectroscopy (“SIMS”): SIMS analysis wasused to determine the presence of trace elements in SOG films. First,the SOG films were measured using a Cameca SIMS device having ppbdetection limits. The use of the resistive anode encoder (RAE) ionimaging detector receives input from the Cameca device and compiles datasuch as trace ion element concentration with time which is used togenerate direct ion maps of any element on the film surface and changesin the lateral distribution of the element as a function of film depth.

[0084] The SIMS analysis was performed using a PHI-6600 quadrupole massspectrometer in which the film was exposed to oxygen and cesium primaryion bombardments with a net impact energy of 6 KeV in order to obtainboth positive and negative secondary ion mass spectrometries. Theanalytical conditions are reported in Table 1: TABLE 1 Primary ion beamOxygen Cesium Primary Beam Energy  6 KeV  6 KeV Beam current 50 nA  20nA  Raster size 150 × 150 μm 150 × 150 μm Analyzed Area 45 × 45 μm 45 ×45 μm Secondary ion polarity + − Charge Neutralization on on Massresolution 300 300

[0085] The data have been plotted as concentration (atoms/cm³) versusdepth for the analytes. The conversion of secondary ion counts toconcentrations is based on a relative sensitivity factors (RSFs) derivedfrom the analyses of ion implant standards of known dose in SiO₂. Theanalytes' secondary ion counts were ratioed to average matrix³⁰ Sisignal through oxide. The reproducibility of analysis typically is lessthan ±10% at ion counting rates above 1×10³. The sputter depth wascalibrated by measuring a crater depth using Tencor P-10 surfaceprofiler. Additional specifics of this technique is further described inbrochures published by Charles Evans and Associates (October 1993).

EXAMPLES Example 1 Preparation of SOG coated Substrate

[0086] A silicon wafer having a diameter of 6 inches was coated with asiloxane SOG available from AlliedSignal Inc. under the tradename“Accuglass” 311 by dispensing about 3 ml to about 4 ml of SOG onto thesurface of the wafer, which was then spun on a SOG coater trackavailable from Dai Nippon Screen, Inc. at about 350 rpm for 2 seconds at72° F., 20-30 mmHg, and a spin cup humidity of 40%. After the coatedwafer was additionally spun at about 3000 rpm for about 20 seconds undersimilar conditions, the wafer was then heated on hot plates in the DNSSOG coater track for three consecutive intervals of 120 seconds at 80°C., 120° C., and 175° C., respectively.

Example 2 Thermal Cure of SOG Coated Wafer (Comparative)

[0087] A wafer produced according to Example 1 was then cured in aBlack-Max-type furnace available from MRL Industries for 1 hour at 425°C. and 1 atm in the presence of nitrogen.

[0088] Analysis of the resulting coated wafer indicated a film thickness(post-cure) of 3000 Å, a film shrinkage of 7%, and a wet etch rate ofabout 37 Å/sec.

Example 3 Electron Beam Cure of SOG Coated Wafer

[0089] Wafers produced according to Example 1 were placed into a chamberavailable from ElectronVision under the tradename “ElectronCure”™ andexposed to an electron beam having a current of 8 to 20 mA, a dose from1000 to 10000 μC/cm² and an accelerating voltage from 5 to 25 KeV, inthe presence of various gases including nitrogen, oxygen, argon, andhydrogen, respectively, and under a temperature from 25 to 400° C. and apressure range from 10 to 40 mtorr.

[0090] Analysis of the electron-beam cured SOG coated wafers indicated afilm shrinkage of 10-30%, and a wet etch rate in buffered oxide etch in50:1 (deionized water: hydrofluoric acid (“HF”)) solution of 1-11 Å/secdepending upon the dose, energy and temperature selected.

[0091]FIG. 1 illustrates the FTIR spectra for wafers thermally curedaccording to Example 2, electron-beam cured according to Example 3, anduncured, i.e. hot-baked, according to Example 1. As evidenced by theabsence in absorbance increases indicating CH stretching modes in theFTIR spectra of FIG. 1 and the homogeneous distribution of carbon asindicated by the carbon peak in the SIMS spectra of FIG. 13, it isapparent that the composition of the films after exposure to electronbeam processing has changed and that the water was not absorbed therein.

Example 4 Wafers Cured at Varying Temperatures and Doses of ElectronBeam

[0092] Wafers were produced according to Example 1 and cured accordingto Example 3 except that each wafer was exposed to one of four doses of1000, 3000, 5000, or 10000 μC/cm² at an energy of 10 KeV under atemperature of either 25° C., 250° C., or 400° C. in the presence ofargon gas.

[0093] FIGS. 2(a) and 2(b) illustrates the FTIR spectra for each of thewafers produced according to Example 4. As evidenced by the increase inabsorbance between 3600 and 3700 cm⁻¹ in FIG. 2(a), wafers which wereexposed to 1000 and 3000 μC/cm² at any of the three temperatures showedhydroxyl group stretching, which is indicative of the presence ofresidual water in the film. However, by increasing electron beam doseequal to or greater than 5000° C./cm², the water in the film can begreatly reduced or entirely eliminated, as illustrated in FIG. 2(b).

Example 5 Comparison of Film Shrinkage for Electron Beam Cured Wafers atVarying Doses, Energies and Temperatures and for Thermally Cured Wafers

[0094] Wafers were produced and cured according to Examples 1 and 3,then were analyzed for film shrinkage by measuring the film thicknessafter bake and electron beam cure.

[0095]FIG. 3 illustrates the film shrinkage as a function of electronbeam doses at temperatures of 25° C., 250° C. and 400° C. in comparisonwith the film shrinkage of the thermally cured films. FIG. 4 shows thefilm shrinkage versus electron beam energy. It is apparent from FIGS. 3and 4 that the shrinkage of electron beam cured films is generallygreater than that of thermally cured films. Furthermore, as the doseincreases, the film shrinkage for the electron beam cured films alsoincreases. In addition, the influence of temperature upon film shrinkagewas observed only for films cured with low electron beam doses; however,film shrinkage was relatively insensitive to variations in electron beamradiation at doses in excess of 10000 μC/cm² and temperatures above 400°C.

Example 6 Comparison of Wet Etch Rates for Electron Beam Cured Wafers atVarying Doses and Temperatures for SOG, Thermal Oxide, andThermally-Cured SOG Wafers

[0096] Wafers were produced and cured according to Examples 1 and 3,then were analyzed for Wet Etch Rate.

[0097] On an uncoated wafer, a thermal oxide film was grown in adiffusion furnace such as those referenced in Example 2 under atemperature of about 1050° C. and atmospheric pressure in the presenceof oxygen at a gas flow of 4 liters/minute.

[0098] Wet etch rates of various films in buffered oxide etch in 50:1solution was determined by measuring the remaining film thickness afterevery immersion in the solution for 1 to 5 minutes depending upon thewet etch rate of the film.

[0099]FIG. 5 presents the wet etch rate versus dose for the electronbeam cured wafers in addition to the wet etch rate for the thermallycured wafer and the thermal oxide wafer. It is evident from FIG. 5 thatthe wet etch rate of SOG coated wafers cured with electron beams is inthe range of 3 to 5 Å/sec., which is very close to the 3 Å/sec etch ratemeasured for the thermal oxide wafer, but is considerably lower than the37 Å/sec etch rate measured for the thermally cured SOG wafers. The lowetch rate demonstrated by the SOG coated wafers indicates that such SOGfilms are significantly more dense in comparison to the thermally grownoxide films.

[0100] FIGS. 6(a) to (d) illustrate the variation of wet etch rate withthe depth of film thickness for electron beam cured films at doses of1000, 3000, 5000 and 10000 μC/cm², respectively. It is apparent fromFIGS. 6(a) and 6(b) that the wet etch rates for films cured undertemperature conditions ranging between 25° C. to 400° C. and a dose of1000 μC/cm² as well as for films cured at a temperature of 25° C. and adose of 3000 μC/cm² were relatively constant throughout the entirethickness of the film. This consistency in wet etch rate valuesindicates that it is possible to produce films having a highly uniformdensity using the above electron beam process conditions.

[0101] As illustrated in FIGS. 6(b) through 6(d), the wet etch rateincreases with the increase in film thickness up to about 1500 Å andthen remained relatively constant for films cured at temperatures of250° C. through 400° C. and a dose of 3000 μC/cm² as well as for filmscured at any temperature and a dose equal to or higher than 5000 μC/cm².

[0102] Similarly, FIG. 7 shows that the wet etch rates for films curedat a temperature of 400° C., an electron beam energy ranging between 5KeV and 25 KeV, and a dose of 1000 μC/cm² are also relatively constant.

Example 7 FTIR Results for Electron Beam Cured Wafers Subjected toChemical-Mechanical Polish Followed by Oxygen Plasma Ashing

[0103] Coated wafers were produced and cured according to the processset forth in Examples 1 and 3, then polished and cleaned with HFaccording to the process set forth in Example 13, followed by ashingwith oxygen plasma. The detail of oxygen plasma ashing is described in,for example, C. K. Wang, et al., “A Study of Plasma Treatments onSiloxane SOG”, VIMIC Conference (June 1994).

[0104]FIG. 8 presents the FTIR spectra for these films at various stagesof curing: (1): after curing with electron beam radiation at a dose of10000 μC/cm² and a temperature of 200° C.; (2): after the cured film ofStage (1) was subjected to chemical-mechanical polish (“CMP”) followedby wet clean in HF solution and oxygen plasma ashing; (3): after threeday's exposure in ambient conditions following Stage (2); and (4): afterre-exposure to electron beam radiation under the conditions of Stage (1)following the ambient exposure of Stage (3).

[0105]FIG. 8 illustrates an increase in absorbance at wavelengthsbetween 3600 and 3700 cm⁻¹ which is indicative of hydroxyl stretching inthe films and thus an increase in the film's moisture intake. Thehydroxyl group stretching is particularly apparent after the CMP andclean processes of Stage (2). However, this moisture could be removed byre-exposure of the films to electron beam processing as shown in FIG. 8.

Example 8 FTIR Results for Electron Beam Cured Films After Exposure toAmbient Environment and Optional Immersion in Water

[0106] After producing and curing wafers according to the processes setforth in Examples 1, 2 and 3, FTIR analysis was performed.

[0107]FIG. 9 compares the FTIR spectrum for a wafer thermally cured inthe presence of nitrogen and at a temperature of 425° C. for 1 hour withthat of a wafer cured with an electron beam at a dose of 10000 μC/cm²and a temperature of 200° C. and exposed to ambient moisture conditionsfor 7 days. The absence of the absorbance increases at wavelengths of3600-3700 (cm⁻¹) for the electron-beam cured wafers illustrates thatthey, in contrast to thermally-cured films, did not absorb moisture.

[0108] FIGS. 10(a) and (b) compare the FTIR spectra for films cured withelectron beam radiation in the presence of argon gas at a dose of 10000μC/cm² and at a temperature of 400° C., and at various energy levelsboth before and after a 24-hour immersion in water having a temperatureof 25° C. respectively. The absence of a visible difference in the FTIRspectra before and after immersion in water indicates that the electronbeam cured films did not absorb moisture when immersed in water for 24hours.

Example 9 FTIR Results for Electron Beam Cured Films Under Nitrogen,Argon, Helium, and Oxygen Environments

[0109] Wafers were produced and cured according to the processes setforth in Examples 1, 2 and 3, with the exception that the films wereexposed to electron beam energy at a dose of 10000 μC/cm² and atemperature of 200° C. in the presence of Nitrogen, Argon, Helium, andOxygen, respectively. After these wafers were aged by exposure toambient moisture conditions for 7 days, FTIR analysis was performed.

[0110]FIG. 11 illustrates a minimal increase in absorbance atwavelengths of 3600-3700 (cm⁻¹) for all gases except Helium. Thus, it isapparent that films may be cured in the presence of Nitrogen, Argon, andOxygen without being susceptible to subsequent absorption of moisture.

Example 10 Chemical-Mechanical Polishing of Electron-Beam Cured Wafers

[0111] Wafers were produced and cured according to the processes setforth in Example 4, then polished and cleaned according to the processesset forth in Examples 7 and 13. During post-polish cleaning,contaminates were removed from film surfaces with a brief oxide etch inHF. This HF dip typically decorates the low density seams in plasmaTEOS, requiring a cap deposition to smooth them over.

[0112] Thickness measurements of the CMP processed films demonstratedthat the electron-beam cured siloxane material possessed awell-controlled polish rate which was similar to that of undoped TEOS,and did not exhibit any high etch rate areas in the post polish cleanedfilm.

Example 11 Disposable Post Device Wafers

[0113] 0.5 μm CMOS SRAM disposable post process device wafers availablefrom Cypress Semiconductor Inc. were coated twice according to theprocess set forth in Example 1, then cured at temperatures of either150, 250, or 300° C. and a dose of 5000, 7500, and 10,000 μC/cm²according to the procedure set forth in Example 4. General details ofdisposable post processing are described in, for example, Cleeves, M.,et al., IEEE Symposium on VLSI Technology Digest of Technical Papers, 61(1994).

[0114] The thickness of the resulting “double coat” on the wafers wasabout 6500 Å. After polishing and processing the resulting wafersthrough an ash, followed by cleaning with HF as described in Examples 7and 13, a Ti—TiW glue layer was deposited directly on the polished SOGsurface of the wafers. Subsequently, the wafers were exposed to a 600°C. rapid thermal anneal (“RTA”) for 1 minute prior to tungsten chemicalvapor deposition (“CVD W”) at 450° C. No lifting or outgassing of thefilm was observed in the resulting wafers.

[0115] The electron-beam cured “double coated” films also were baked for30 minutes in a furnace set a temperature between 425° C. and 700° C.Film shrinkage analysis of films baked at a temperature of 425° C.indicated a 4% shrinkage in thickness based upon the thickness asmeasured directly after rapid thermal anneal. No additional shrinkageoccurred at temperatures up to 700° C. Therefore, it is apparent fromExample 11 that the amount of film shrinkage is independent oftemperature. Moreover, the resulting wafers were crack-free andwell-planarized.

Example 12 Etched Contact Device Wafers

[0116] 0.5 μm CMOS SRAM conventional etched contact device wafers wereproduced, cured, polished, cleaned according to the procedure set forthin Example 11, with the exception that both single-coated anddouble-coated wafers were prepared. No lifting or outgassing of thefilms was observed during all the process steps required for thefabrication of these devices.

Example 13 Direct On Metal CMP Wafers

[0117] Two coats of Accuglass® 311 SOG were deposited directly onsilicon wafers patterned with metal 1, i.e. aluminum, and cured with anelectron beam according to the conditions as described in Example 4.9,000 Å of TEOS was deposited in the manner of CVD onto the resultingSOG layer then polished using a Ipec Westech polishing machine equippedwith an IC 1000/SUBA 4 polish pad available from Rodel under thefollowing conditions: wafer pressure of 7 psi; polish temperature ofwafer of 110° F.; SC 112 slurry available from Rippey flowing at 130ml/min.; platen (holding pad) rpm of 28; carrier (holding wafer) rpm of28; polish position of 185 mm; and platen oscillations of 5 mm at aspeed of 2 mm/sec. Wafers were polished and cleaned with HF, followed byashing with oxygen plasma. No adhesion problems or other undesirableinteractions were seen between the SOG and TEOS layers.

[0118] In order to expose the interface between the SOG layer and theTEOS layer to polish stresses, the wafers produced in this Example weresubsequently polished under similar conditions. No delamination or otheranomaly was observed.

Example 14 Variable Number of SOG Layers on Metal With Exposed Interface

[0119] Example 13 was repeated using either one, two, or three coats ofSOG on the wafers. These wafers also showed excellent planarizationwithout cracking of the SOG layer.

Example 15 TEOS-Capped. Variable Number of SOG Layered Wafers

[0120] TEOS-capped wafers were produced and cured according to processesset forth in Examples 13 and 14, but with the exception of using about12,000 Å of a doped TEOS oxide dielectric over the active devices, adose of 5000 and 10000 μC/cm² and an energy of 9 and 15 KeV. The energyrequired for the electrons to reach the surface of the wafer wasestimated to be about 12 KeV. The chosen values of electron beam energywere thus expected to put electrons beyond the TEOS film's surface andinto the silicon wafer itself.

[0121] The cured wafers were then processed through the contact etch,contact fill (W plug) and local interconnect formation steps as setforth in Example 11, and tested for device and field threshold voltagesand QBD of the gate oxide. The details of these tests are described inWolf, “The Submicron MOSFET”, 3 Silicon Processing for the VLSI Era(1995). The results of the field threshold test did not indicate a shiftin the voltage (“Vts”) of the n-channel transistors, but showed a smallshift in the Vts of the p-channel transistors. However, the 30 mV shiftof Vts of the p-channel devices at high energies of 15 KeV is stillsmall in comparison to the permitted range for Vt variation, i.e. up toabout 150 mV. An increase in the dose over 10000 μC/cm² with electronbeam energy of 15000 KeV resulted in a systematic degradation of theQBD, which implies that the gate oxide may become damaged duringelectron beam exposure at such high levels.

Example 16 Characteristics of SRAM Test Structure Incorporating Film asa Dielectric Over Polysilicon

[0122] A “double coat” of Accuglass® SOG film was produced and curedonto 0.5 μm polysilicon-coated Static Random Access Memory (“SRAM”) teststructures in accordance with the procedure set forth in Example 3 andunder conditions of 200° C., 10 KeV, and 10000 μC/cm². 0.6 μm contactswere then made in the cured SOG coated structures by either theconventional etch based approach of Example 12 or the disposable postprocess of Example 11.

[0123] In the post processed structures, SOG characteristics wereevaluated at different temperatures of anneal, i.e. 425° C., 600° C.,and 700° C. before contact metallization but after formation of thecontacts. The salicide resistance was unaffected by the SOG processbecause of the low thermal budget.

[0124] In order to form vias by conventional etch processes, the SOGlayer was capped by 9000 Å of TEOS SiO₂ as described in Examples 13 and14, then polished back according to the process set forth in Example 13.0.7 vias were etched in this dielectric. Via filling was performed withblanket W and etchback processing as described in, for example, H.Kojima et al., “Planarization Process Using a Multi-Coating ofSpin-On-Glass” VLSI, (June 1988).

[0125] Electrical resistance tests as described in, for example, Anner,“Planar Processing Primer” 79-90 (1990), of the structures containingetch contacts showed that the contact resistance of the electron-beamcured SOG layer was higher than that for the doped reflowed TEOS SiO₂dielectric layer. This is likely due to the large overetch in thecontact etch which etched away most of the TiSi₂ from the underlyingoxide.

[0126] As illustrated in FIG. 12, the QBD of the gate oxide isequivalent to that of doped reflowed TEOS SiO₂ with etched contacts,which implies that the damage to the oxide during electron-beamprocessing for wafers having a thin SOG layer is less than that forwafers having a TEOS SiO₂ oxide. A summary of the electrical results isprovided in Table 2. TABLE 2 Contact resistance (ohms) Self- SalicideSelf- Self- aligned P⁺-N⁺ Generic Generic aligned aligned ContactSalicide strap Contact scheme to N⁺ to P⁺ (P⁺) (N⁺) Leakage resistanceresistance Post scheme 38 36 42 48 Pass 16 170 with SOG (425 C Anneal)Post scheme 39 High open 61 Pass 19 270 with SOG (600 C Anneal) Postscheme 37 35 45 50 Pass 22 205 with SOG (700 C Anneal) Etch scheme 32 31NA NA NA 30 180 with SOG Control 25 25 68 58 Pass 135 >5000

Example 17 Electron-Beam Processed

[0127] CVD TEOS for Poly Level Dielectric

[0128] A layer of TEOS film having a thickness between 1000 Å to 8000 Å,preferably from about 1500 Å to about 3000 Å, is deposited via CVD ontopolysilicon wafers under a temperature of about 350° C. to about 450° C.and a pressure of about 7 to 9 torr. The TEOS film is then exposed forabout 10 minutes to a flux of electron-beam radiation at a dose of about5000 to about 10000 μC/cm² and an energy of about 5 to about 15 KeVunder a temperature of about 200° C. to about 250° C. and a pressure ofabout 10 mTorr to 40 mTorr in the presence of nitrogen or argon in anElectronCure™device available from from Electron Vision, Inc. Theresulting film is a silicon-rich, densified TEOS oxide.

[0129] Either silicate, phosphosilicate, and or siloxane SOG is thenspun-on the cured TEOS wafers and cured. The type of SOG selected andthe thickness of the SOG coating is dependent upon the desiredplanarization. Optionally, the dielectric stack may be completed by aCVD TEOS oxide deposition if desired, or alternatively, the SOG may beleft as the final layer in the inter-level dielectric stack.

Example 18 Formation of Ultra-Thin Gate Oxide

[0130] Polysilicon wafers are exposed to the electron beam processingconditions of Example 15 in the presence of oxygen gas under pressuresof about 10 to about 200 mTorr and temperatures of about 250° C. for aperiod of time sufficient to grow the desired thickness of oxide. Theresult is a uniformly dense and homogeneous film which is suitable forfurther processing required for microelectronic applications.

1. A process for curing a dielectric material on a substrate comprising:(a) applying to a surface of said substrate a dielectric material; and(b) exposing said dielectric material to electron beam radiation underconditions sufficient to cure the dielectric material into a filmpossessing desired characteristics.
 2. The process of claim 2 whereinsaid dielectric material is comprised of silicates, phosphosilicates,siloxanes, phosphosiloxianes or mixtures thereof.
 3. The process ofclaim 2 wherein said dielectric material is comprised of, beforeexposure to said electron beam radiation, a siloxane having, based uponthe total weight of said siloxane, of from about 2% to about 90% oforganic groups comprising alkyl groups having from about 1 to about 10carbons, aromatic groups having from about 4 to about 10 carbons,aliphatic groups having from about 4 to about 10 carbons, or mixturesthereof.
 4. The process of claim 2 wherein said dielectric material iscomprised of, based upon the total weight of said dielectric material,from about 0% to about 10% phosphorus.
 5. The process of claim 1 whereinsaid dielectric material is applied to said substrate via spin-coating.6. The process of claim 1 wherein said film has a thickness of fromabout 500 Å to about 20000 Å.
 7. The process of claim 1 wherein saiddielectric material is cured at a temperature of from about 25° C. toabout 400° C.
 8. The process of claim 1 wherein said dielectric materialis cured at a pressure of from about 10 mtorr to about 200 mtorr.
 9. Theprocess of claim 1 wherein said substrate is preheated with atemperature of from about 50° C. to about 250° C. before said dielectricmaterial is exposed to electron beam radiation.
 10. The process of claim1 wherein said substrate is exposed to electron beam radiation in thepresence of a gas selected from the group consisting of oxygen, argon,nitrogen, helium and mixtures thereof.
 11. A film produced according tothe process of claim
 1. 12. A substrate coated with at least one layerof the film of claim
 1. 13. A microelectronic device containing thesubstrate of claim
 12. 14. A process for annealing a substrate coatedwith a chemical vapor deposit material comprising: a) applying to thesurface of the substrate the chemical vapor deposit material; and b)exposing the chemical vapor deposit material to electron beam radiationunder conditions sufficient to anneal the chemical vapor depositmaterial into a film possessing desired characteristics.
 15. The processof claim 14 wherein said chemical vapor deposit material is comprised ofplasma-enhanced tetra-ethyl ortho silicate, silane based oxide,boron-phosphosilicate glass, phosphosilicate glass, nitride, anhydridefilm, oxynitride, borophospho glass from tetraethyl orthosilane, ormixtures thereof.
 16. The process of claim 14 wherein said chemicalvapor deposit material is a silane-based oxide.
 17. The process of claim14 wherein said chemical vapor deposit material is applied to saidsubstrate in the presence of a gas comprising a mixture of tetra-ethylortho silicate and oxygen or oxygen, silane and optionally diborane,phosphine, and nitrous oxide.
 18. The process of claim 14 wherein saidchemical vapor deposit material is applied to said substrate viaspin-coating.
 19. The process of claim 14 wherein said film has athickness of from about 500 Å to about 20000 Å.
 20. The process of claim14 wherein said chemical vapor deposit material is annealed at atemperature of from about 25° C. to about 400° C.
 21. The process ofclaim 14 wherein said chemical vapor deposit material is annealed at apressure of from about 10 mtorr to about 200 mtorr.
 22. The process ofclaim 14 wherein said substrate is preheated to a temperature of fromabout 50° C. to about 250° C. before exposure to electron beamradiation.
 23. The process of claim 14 wherein said substrate is exposedto electron beam radiation in the presence of a gas selected from thegroup consisting of oxygen, argon, nitrogen, helium and mixturesthereof.
 24. A film produced according to the process of claim
 14. 25. Asubstrate coated with at least one layer of the film of claim
 24. 26. Amicroelectronic device containing the substrate of claim
 24. 27. Aprocess for growing ultra-thin film oxides or nitrides on a substratecomprising: (a) exposing a surface of the substrate to electron beamradiation in the presence of a material in a gaseous state and underconditions sufficient to ionize the material and promote an oxidizationor nitridation reaction on the surface of the substrate.
 28. The processof claim 27 wherein said substrate is comprised of gallium arsenide orsilicon.
 29. The process of claim 28 wherein said substrate is comprisedof crystalline silicon, polysilicon, amorphous silicon, epitaixalsilicon, or silicon dioxide.
 30. The process of claim 27 wherein saidmaterial is comprised of oxygen, ammonia, nitrogen, nitrous oxide,reaction products or mixtures thereof in the form of a gas, a sublimedsolid or a vaporized liquid.
 31. The process of claim 27 wherein saidoxides or nitrides are grown on said substrate simultaneously while saidsubstrate is exposed to electron beam radiation.
 32. The process ofclaim 27 wherein said ultra-thin film oxides or nitrides have athickness of from about 10 Å to about 1000 Å.
 33. The process of claim27 wherein said material is ionized at a temperature of from about 25°C. to about 400° C.
 34. The process of claim 27 wherein said material isionized at a pressure of from about 10 mtorr to about 200 mtorr.
 35. Theprocess of claim 27 wherein said substrate is preheated to a temperatureof from about 50° C. to about 250° C. before exposure to electron beamradiation.
 36. An ultra-thin film oxide or nitride produced according tothe process of claim
 27. 37. A substrate coated with at least one layerof the film of claim
 36. 38. A microelectronic device containing thesubstrate of claim
 37. 39. A process for reducing the dielectricconstant in substrates coated with a dielectric material comprised ofexposing said material to electron beam radiation under conditionssufficient to cure said material.
 40. A process for reducing thedielectric constant in substrates coated with a chemical vapor depositmaterial comprised of exposing said material to electron beam radiationunder conditions sufficient to cure said material.
 41. A microelectronicdevice containing a substrate coated with a film which was exposed toelectron beam radiation, wherein the dielectric constant of saidelectron-beam processed film is less than about
 3. 42. The process ofclaim 1 wherein said dielectric material is exposed to electron beamradiation for about 2 minutes to about 45 minutes.
 43. The process ofclaim 1 wherein said substrate is a silicon wafer.
 44. The process ofclaim 14 wherein said substrate is a silicon wafer.
 45. The process ofclaim 27 wherein said substrate is a silicon wafer.